1. Field of the Invention
This invention is directed to a mapped memory system, in general, and, more particularly, to a mapped memory system wherein higher speed of operation is obtained with no performance penalty.
2. Prior Art
Memory mapping techniques are known in the art. These techniques are utilized in order to effectively enlarge the memory content of the actual memory system capabilities. With mapping techniques, may arrays are provided to establish virtual memories which can be accessed or addressed through the map memory thereby increasing the apparent storage capacity and addressing capability of the system. In addition, the technique provides logical address space for programs in a multi-program and multi-tasking environment.
In the known mapping techniques, the central processor unit (CPU) supplies an address to the map array which performs the appropriate mapping technique. The map array then reformats the address word and applies this reformatted word to the memory to perform the appropriate function such as fetching the appropriate information in the memory portion addressed. However, this technique is relatively time consuming and expensive in terms of the hardware and components which are utilized in the system.